Piplin documentation

(: Refer - clojure: as clj: exclude [not = bit - or - bit - xor + - * bit - and inc dec?

Piplin's overview provides a simple tutorial that will help you get started. Reading and examining the example code provided will take about 30 minutes.

This guide explains how to use the same function and type in REPL, simulation, and generated Verilog. We introduce simple types and intensive types, and how they are constructed and interacted.

Explain the Piplin module system Describes how to declare modules, how to combine state loops and feedback loops in your design, and how to combine modules to create more complex designs.

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The basic idea of ​​the Piplin module is that all cycles, all inputs are registers, their values ​​are read. After that all logic is executed and the register value of the next cycle is determined. This is repeated permanently (in hardware) or with a fixed number of loops (in simulation). The logic is specified as a graphic in the first map, and the register and its default value are specified in the second map. Here we introduce the bit type of Piplin. # B00_00 is the syntax for declaring bit literals. The underscore has no meaning. It's just to use as a visual delimiter. In this example, you need to provide an input called direction. This is a Boolean value to synthesize it. Let's make another module to provide direction

Piplin is an excellent way to describe hardware structures using knowledge of programming, algorithms, and JVM libraries. It helps to understand computer architecture and registered digital logic. The following is a brief introduction to the digital logic. Because Piplin does it automatically, I recommend you skip the Karnaugh map description. The basic idea of ​​the Piplin module is that all cycles, all inputs are registers, their values ​​are read. After that all logic is executed and the register value of the next cycle is determined. This is repeated permanently (in hardware) or with a fixed number of loops (in simulation). The logic is specified as a graphic in the first map, and the register and its default value are specified in the second map.