Design of a New Full Adder for Fast Arithmetic Operation Processing

Introduction Addition is the most important function of digital systems. The adder is used only for arithmetic operations, but it is also necessary for all modern computers. Adder occupies critical path in important areas of microprocessor and high speed adder is the main requirement for high speed processing system design. Although many high-speed adders are prepared, it is still difficult to design high speed, low power consumption, and small area adder. In modern computers, multiple ALUs with wide adder and multiple execution core units on the same chip create hot spots and large temperature gradients.

The adder is a digital circuit that performs digital addition. For many computers and other types of processors, the adder is used in arithmetic logic units or ALUs. They are also used in other parts of the processor to calculate addresses, table indexes, increment and decrement operators, and so on. Although it is possible to build an adder for many digital representations such as binary coded decimal numbers or numbers greater than 3, the most common adder works on binary numbers. If you use two's complement or one's complement to represent a negative number, the adder is changed to an adder. The subtractor is simple. Other signed numbers indicate more logic around the basic adder

Adding two binary numbers is the most basic arithmetic operation, 2 bits. A combinatorial circuit that can only add 2 bits is called a half adder. A full adder is a full adder that adds two or more digits, that is, three digits. The full adder uses two adders for its implementation. In this survey, the full adder is the basic addition used in all adders. Half is a basic addition circuit that performs 2-bit addition and outputs sum and carry. Half adder circuit uses XOR and AND gates for addition and carry output. The XOR gate outputs and the carry output is given by the AND gate. X and Y are input S in total, C 0 is carry

Although the layout of the ripple carry adder can be designed simply and quickly, the ripple carry adder is relatively slow because each full adder has to wait for the carry from the previous full adder. The gate delay can be easily calculated by examining the full adder circuit. Each full adder requires three levels of logic. In the 32-bit ripple carry adder, there are 32 full adders, so the delay of the critical path (in the worst case) is 3 (from the input to the first adder carry) + 31 × 2 (the latter in the adder). Carry propagation) = 65 delay. The general expression for the worst-case delay of the n-bit carry ripple adder, sum bit, and carry bit is: